A 32x32 SPAD Pixel Array with Nanosecond Gating and Analog Readout

CMOS Single Photon Avalanche Diode (SPAD) arrays are emerging as appealing solid-state detectors in imaging applications where high sensitivity and timing resolution are required. In this work, a 32x32-pixel array where SPAD digital output is processed in the analog domain in a 12-transistor pixel is presented. A 25m pixel pitch with a remarkable 20.8% fill factor was achieved thanks to a very compact pixel electronics, and gating pulse widths down to 1.1ns FWHM at 80MHz repetition rate were demonstrated. INTRODUCTION Among solid-state detectors, SPADs offer unique features such as single photon detection capabilities and picosecond timing resolution [1], which are jointly present only in photomultipliers and micro-channel plates. A rugged and costeffective solid-state alternative to these detectors would be highly desirable in application fields such as fluorescence imaging and time-of-flight optical ranging. Although the CMOS integration of SPADs was demonstrated several years ago, the design of effective SPAD-based pixels for imaging applications still presents many challenges: since each SPAD produces a digital pulse for every detected photon, a complex electronic circuit should be implemented at the pixel level to perform data storage while preserving timing information in a small area and with a reasonable fill factor. SPAD-based image sensors presented so far [2-5], despite offering additional functionalities and excellent timing resolutions with respect to standard pixels, feature fill factors in the order of some percent, which spoil their overall efficiency and are difficult to recover by means of optical concentrator arrays. In this work, a compact SPAD-based pixel is presented, which includes an analog gated counter in a 25m pitch with a state-of-the art fill factor of 20.8%. A 32x32 pixel array was implemented in a 0.35m High Voltage CMOS technology together with a digital PLL for on-chip nanosecond gating signal generation. DESIGN The all-NMOS 12-transistor pixel presented here includes a passively quenched SPAD, an inverter working as a digital comparator, a gating circuit and an analog counter (Fig. 1). A compact pixel layout was possible because both the SPADs and the ptub including the n-type MOSFETs were integrated in the same deep-ntub, as shown in Fig. 2. The pixel working principle is illustrated in Fig. 3. A 5V quenching transistor (M1) determines the recharge time of the SPAD after each avalanche event. Transistor M2 is used to clamp the voltage pulse at node B, allowing the use of 3.3-V transistors in the next part of the circuit. In this way, excess bias voltages larger than 3.3V can be used to bias the SPAD without damaging the inverter. Each avalanche event generates a positive pulse at node B and a negative and slightly delayed pulse at node C, after passing through the inverter formed by M4 and M5. Transistor M3 was included for testing purposes to generate an electrical pulse simulating an avalanche event. If the event occurs inside the time window WIN, a negative picosecond voltage pulse is generated by the gating circuit, formed by transistors M6, M7 and M8. This pulse removes a small charge packet from the integration capacitor through transistor M9, generating a voltage step V at node E (Fig. 3b). If the event occurs outside the gating window WIN, the pulse is not generated and the event is not counted (Fig. 3a). The value of V can be set through the reference voltage VbAC. The final part of the pixel is composed of a reset transistor (M10), a source follower (M11) and a select switch (M12) as in a standard 3T active pixel. Therefore, the pixel output can be read-out as in a common active pixel image sensor. A digital PLL working at a maximum frequency of 40MHz was also implemented on-chip for gating signal (WIN) generation. Fast gating signals can be also provided externally for maximum flexibility. The floorplan and the layout of the sensor are shown in Fig. 4 and 5 respectively. CHARACTERIZATION A typical pixel output voltage oscilloscope trace, where each counted photon corresponds to a voltage step V, is shown in Fig. 6. The output voltage histogram, obtained from 10000 acquisitions of a single pixel, is shown in Fig. 7. The histogram shows that single photons can be resolved and therefore shot noise limited operation is maintained even if the pixel is operating in the analog domain. An 11% non-uniformity in the voltage step V among the pixels is R40